for Intel QuickPath interconnect, FBD2 DDR3 or PCI Express High-Speed Routing in Cadence Allegro. The program will automatically reduce the cline width just before and after targeted pins and vias. Increases the trace impedance, compensating for the decrease in impedance caused by pin and via connections. Can target pins, vias or both, with the option to target mid-route vias. Can exclude fanout vias on a user defined list of devices where special routing should not be modified. Automatic and interactive modes. |
Before Cline Neck Down | After Cline Neck Down |
Quickly review each cline reduction using the report window. |