Copyright 2000-2010 CopperCAD Design Inc.


Table of Contents

1 PURPOSE:
2 FEATURES:
2.1 USING METS (Graphical/Interactive mode):
2.1.1 Button "Area= ???".
2.1.2 Button "SolderFlow= ???".
2.1.3 Button "Load_Parameter".
2.1.4 Button "Create_Parameter".
2.1.5 Button "Display_VIOL".
2.1.6 Button "Verify".
2.1.7 Button "AutoRUN".
2.1.8 Available Function Keys.
2.2 USING METS ( NON-GRAPHICAL MODE ):
3 REQUIREMENTS & LIMITATIONS:
4 ADMINISTRATION REQUIREMENTS:
5 HELP - METS.OVERVIEW:
6 PARAMETER FILE:
7 PROGRAM INSTALLATION:
8 LOADING METS:
8.1 Long Term:
8.2 Short Term:
9 KNOWN BUGS:
APPENDIX A
Definition of Terms
APPENDIX B
PARAMETER GROUPS & PARAMETERS FOR REFLOW MANUFACTURING PROCESS:
PARAMETER GROUPS & PARAMETERS FOR GLUE & WAVE MANUFACTURING PROCESS:
PARAMETER GROUPS & PARAMETERS FOR OTHERS:
APPENDIX C
SAMPLE VIOLATION REPORT:

[UP] 1 PURPOSE:

The goal of METS is to provide a seamless tool for the identification, verification, and reporting of Corporate Standard 5015 related rules. Unlike the LAYOUT verify, METS closely models all variances of the 5015 specification, which removes the burden of running with worst case parameter values and being overwhelmed with violations that require manual evaluation.

METS provides two modes of operation, Graphical/Interactive and Non- Graphical. The Graphical/Interactive mode is a LAYOUT based Graphic User Interface (GUI) application that allows calculation, viewing and reporting in an interactive environment. The Non- Graphical mode is a shell script (domrv) that is executed from the UNIX environment. The main purpose of the Non-Graphical mode is to allow the tasks of calculation and reporting without tying up a graphics terminal. Provision is also made to execute in the background to free up a telnet session window.

[UP] 2 FEATURES:

Parameters have default values defined per corp std 5015 (draft NO 1 July 97) and per results of solder conference of May 1994. Clearance/Spacing parameters can be re-defined in an ASCII file referred to as local parameter files. The local parameter file, "<DesignFileName>.mets.parameter", will override default values and become the default value. A warning message will be displayed if there is any difference between the default values and the new values. The TECHNOLOGY's file name is very important since METS will use this file name to determine the board's process: RW, RX, XW or RR. The definitions of the technology files are defined in corp std 5015.00.
Without METS, these violations will not be flagged by LAYOUT's verify:
1. Corp std 5015 minimum spacing requirements:
METS uses the lattest 5015.06 (draft Nov 97) datas to check for the spacing between:
  • Device-bodies to Device-bodies; Device-bodies to Pins; Device-bodies to Vias.

  • Device-pins to Device-pins; Device-pins to Vias.

  • Vias to Vias.

2. Fiducials:
  • Check if devices need fiducials.

  • Check if the quiet zones of the board-fiducials are violated.

3. Silkscreen:
  • Check if device-designations are missing.

  • Check if device-designations are duplicated.

  • Check if device-designations are too far from devices.

  • Check if device-designations placed under devices.

4. Exposed Copper:
  • Check if any copper tracks or planes are exposed.

5. Testpad Accessible:
  • Check if each signal must have at least one testpad.

  • Check if testpads found under devices.

  • Check if testpads have proper solder-resist pads.

  • Check if testpad lands are 40 square mils.

6. Device-pins and Vias integrity:
  • Check if pins and vias have proper solder-resist pads.

7. Drill-wander:
  • Check if copper tracks are placed too close to vias and mounting-holes (Drill bit may cut the tracks).

8. Device-placement:
Depending on the board-flow direction, METS checks if devices are placed properly.
  • Check if device-rotation are against the board's flow.

  • Check if devices are blocking other devices.

9. Glue-dot check:
  • If the board's process is Glue&Wave, METS checks if devices placed on the secondary side have Glue-dots.

10. METS Warning:
METS creates a file called .warning.rep.
  • Any devices carry High-current will get warning message asking users to check if wider copper tracks are needed.

  • Same device Pcodes found on different layers. It is prefered to place devices having same Pcodes on the same layer.

2.1 USING METS (Graphical/Interactive mode):

When METS is activated, a menu is displayed with buttons which users can use the mouse puck1 to activate or puck3 to exit:

2.1.1 Button "Area= ???":
2.1.2 Button "SolderFlow= ???":
If the technology RW, RX or XW is used, the BoardFlow's direction must be determined by users; otherwise, the default will be N->S. The boardFlow's direction can be ignored if the design is using RR (Reflow-Reflow) process. From the BoardFlow's information, METS will check if the device rotations are against the Corp. standard and if devices blocking devices occur.
2.1.3 Button "Load_Parameter":
 If users does not want to use the default parameters (generated by METS), they can tell METS to read other parameter file by selecting this button. Another menu will appear asking user to enter a new parameter file name. METS will open a file named "mets.profile" located at user's HOME directory and read the new path name indicating where to pick up the new parameter file. Please note that users have to create file "mets.profile" at the home directory. For more informations of how to change the parameters please refer to <DesignFileName>.mets.parameter sample.

2.1.4 Button "Create_Parameter":
If user want to "modify" the default parameters, the quick way is to select this button so that the default parameter file is generated. Then the parameter values can be changed by opening the file .mets.parameter.

2.1.5 Button "Display_VIOL":
After running the verification on the board, user can select this button to view the violations. Users can toggle the mouse puck1 to go to the next violation, mouse puck2 to go to the previous violation or mouse puck3 to exit the Display_VIOL mode. Please note that the cursor must be in the Graphic area for this to work.

User can also go directly to any violation number by typing ``Ctrl_V''. User will be asked to enter a violation number which can be found in the <DesignFileName.mets.rep> under column Ref.

2.1.6 Button "Verify":
If users want to run verification interactively, they can select this button. Another menu will appear which give user a selection of choices:

a. PRI+SEC_Layers: This will verify all the surface mount spacings on the PRI and SEC layers.
b. PRI_Layer: This will verify all the surface mount spacings on the PRI layer only.
c. SEC_Layer: This will verify all the surface mount spacings on the SEC layer only.
d. Fiducial_CHK: This will verify if a quiet zone is violated and if a device must have fiducial targets.
e. Silkscreen_CHK:

f. Expose_Copper: This options will check if the exposed copper occur. If the exposed copper is intentional, users can turn off this check changing the parameter "Expos_Copper = NO" in the .mets.parameter.
g. Pad_CHK: If user select this button, the follow checks will be done:
  • TestPad: (Signal/TP) make sure each logic signals must have at least one testpad; (TP/Device) Testpads must not be covered by device body. (TP/Integrity) Testpad size must be at least 40 mils. (TP/SR) Testpad do not have proper solder-resist. (MM_TP) Testpads covered by testpads texts.
  • PinSolderResist: Make sure that device pins, vias and breakoutVias have proper solder-resist pads.
  • FloatSolderPaste: Make sure that only device pins, misc. pins and holes have solder-pastes.
  • PadOffset: If Glue&Wave process is used, this option will check if package 0808 found on the secondary side have the inter-pins spacing of at least 45 mils.
  • GlueDot: If Glue&Wave process is used, this option will check if devices placed on the secondary side have GlueDots.
h. Pcode_CHK: If user select this button, METS will scan the "corp.cd" database to check if the Pcodes used in the design are legitimate.
i. Placed_Component: If user select this button, another menu will appear which give user a selection of choices:
  • TH/PRI: No thru hole device is allowed on the secondary layer.
  • DevRot/SEC:Depending on the "SolderFlow's direction" which user selected, METS will check the device's orientaion as per corp std 5015. This only affect if there is a "WAVE" process applied on the board.
  • DevBlock/SEC: Depending on the "SolderFlow's direction" which user selected, METS will check if a device is "Blocking" another device. Please refer to corp std 5015 for the definition of the "Device Blocking".
  • PowerDev: METS will locate the power devices and warn users if thick copper tracks are needed. The warning message will be found in file .warning.rep.
  • PcodeLayer: METS will give warning message if same device Pcodes found on different layers. The warning message will be found in file .warning.rep.
j. Unicad: If user select this button, another menu will appear which give user a selection of choices:
  • TearDrop: METS will check is any "teardrop" is missing.
  • CopperShort (default NO): If the parameter CopperShort = YES, METS will find if there is any copper-short in the design. Please note that this check may take a long time to run; therefore, it is default to NO.
  • DrillWander: (Drill/PTH) the minimum spacing between copper tracks and vias is 10 mils; (Drill/NPTH) the minimum spacing between copper tracks and non-plated-thruhole is 30 mils; This check is to prevent the drill's bit from cutting the copper tracks.
2.1.7 Button "AutoRUN":
 If user selects this button, METS will verify using ALL the parameters as per "Area" and "SolderFlow" defined by users.

2.1.8 Available Function Keys:
  • PF2: Zoom Home.
  • PF4, PF6: Zoom In.
  • PF5: Zoom Out.
  • PF7: Screen Refresh.

2.2 USING METS ( NON-GRAPHICAL MODE ):

 This is a UNIX shell script (domrv) which will execute the sprig/layout and METS.p without the need of a graphics terminal. Both <DesignFileName>.viol and <DesignFileName>.rep files will be generated.

2.2.1 A user specified parameter file can be specified using '-tech <filename>' option.

2.2.2 The same functonality is provided as with the graphics mode with the exception of displaying violations.

2.2.3 Executing the script name will prompt the user according to what files are found in the current directory.

2.2.4 Executing the script name with a design name as an argument will process only that design. For more informations of how to run domrv, users can type: domrv -h.
Example: domrv -nop <fn.dd> -sysdir <parameterDir> -Tech <BRW.mets.parameter>
This command will run METS on the file fn.dd using parameter file BRW.mets.parameter which is located in the directory parameterDir. Users can also set up a batch program to start domrv at any time.

2.3 METS REPORTS:

After running the verifications, METS creates new files:
  • DesignFileName.mets.rep: This report contains violations found.
  • DesignFileName.warning.rep: This report contains warning messages only.
  • DesignFileName.viol: When users want to display violations, this file is needed.
  • DesignFileName.mets.parameter: This file contains spacing parameters. Users can open this file and change the parameters if needed.

[UP] 3 REQUIREMENTS & LIMITATIONS:

3.1 METS currently requires CBDS 5.03.00 or higher on a Apollo/HP/Sun workstation.

3.2 This software is intended to be invoked in a directory that contains one or more design file(s). Multiple sessions of METS are allowed on a workstation as long as each is in a separate directory. The output files generated by METS are named by using the UNIX filename of the design file <DesignFileName>.

[UP] 4 ADMINISTRATION REQUIREMENTS:

METS.p will load using AppMan ifit is located in one of the following directories:

4.1 (curent directory)

4.2 /cad/sw/<cad_ver>/sprigdir/ (<cad_ver> must be 50300 or higher)

4.3 /cad/sw/<cad_ver>/cbdslispdir/

4.4 /cad/sw/<cad_ver>/sharedir/

4.5 /cad/sw/<cad_ver>/rfdir/

4.6 /cad/sw/database/

4.7 /tmp

4.8 Should a directory other than specified above be used, then the environment variable CBDS_PATH (UNICAD_PATH for cad 50400 and higher) must be set to that directory. Use the command 'setenv CBDS_PATH <dir_name>' OR 'setenv UNICAD_PATH <dir_name>'

[UP] 5 HELP - METS.OVERVIEW:

5.1 This file can be obtained by using the AppMan help feature in sprig/layout. After help is selected for METS, this file will be displayed using CBDS CADHELP. CADHELP has many features such as printing, and text search facilities that are useful. CADHELP has help information that will explain its operations and features.

[UP] 6 PARAMETER FILE:

6.1 The value for the parameters checked by METS can be re-defined in a parameter file that is similar to the sprig/layout technology file. The definition of parameter naming scheme is defined in Appendix A. Appendix B lists currently identified parameters that need verification against the 5015 corp standards. Note, only a subset of Appendix B is currently being checked. METS uses the parameter values defined within its code as the primary source.

6.2 Each time METS is run a tech file <DesignFileName>.mets.parameter is created or re-created according to the parameter settings at the time. This file can be modified by the user and used as a local parameter file.

[UP] 7 PROGRAM INSTALLATION:

The following files are used for METS

[UP] 8 LOADING METS:

METS is a layout LISP application that is loaded by using the LISP application manager called "AppMan". If "AppMan" and "METS" are not shown as icons at the top of the layout screen, there is a short and long term solution.

8.1 Long Term:

8.1.1 Create/edit the .sprigrc.l file in home directory (.elle NOT .one)

8.1.2 Add the following 3 lines to the file exactly as shown

(setq AppManCBDStool "SPRIG")

(load 'AppMan.p)

(load 'METS.p)

8.1.3 For every new layout session that is invoked, the "AppMan" and "METS" icons should now be loaded automatically.

8.2 Short Term:

8.2.1 Reference the CBDS help topic "Installing CBDS LISP packages" for details on installing "AppMan" and "METS" for this sprig/layout session.

8.2.3 Check with your System Manager if you need assistance with the previous commands.

[UP] 9 KNOWN BUGS:

9.1 Using METS on more than one design from one sprig/layout session with a HP730 workstation usually results with a LISP ERROR occuring with the 'inPolygon' primitive ( :ErrInternal). This could not be duplicated using an Apollo workstation.

9.2 The primitive function 'inBox' will sometimes fail while using CAD version 503. This may be caused by loading a cds file which was created by a different CAD version or some corrupt data is in the cds file. using the utility 'cdstidy' will usually correct this problem.

<DesignFileName>.mets.parameter

Parameter Group 'SM pad to VIA (DIFF sig) - reflow PRI'

SMp-V/r = ((15 15 15 15)(15 15 15 15)) ; SM pad to Via (All) *

SMp-V0603/r = ((13 15 13 15)(15 13 15 13)) ; SM pad to Via (0603) *

SMp-V0805/r = ((18 15 18 15)(15 18 15 18)) ; SM pad to Via (0805) *

SMp-Via/r = ((20 15 20 15)(15 20 15 20)) ; SM pad to Via (1206) *

Parameter Group 'GW pad to VIA (DIFF sig) - reflow PRI'

GWp-VIA/r = ((15 15 15 15)(15 15 15 15)) ; GW pad to Via *

Parameter Group 'CHIPL pad to VIA (DIFF sig) - reflow PRI'

SMp-V1808/r = ((25 15 25 15)(15 25 15 25)) ; SM pad to Via (1808) *

SMp-V1210/r = ((30 15 30 15)(15 30 15 30)) ; SM pad to Via (1210,2010) *

SMp-V1812/r = ((35 15 35 15)(15 35 15 35)) ; SM pad to Via (1812,2512) *

SMp-V2220/r = ((55 15 55 15)(15 55 15 55)) ; SM pad to Via (2220) *

SMp-V2225/r = ((68 15 68 15)(15 68 15 68)) ; SM pad to Via (2225) *

Parameter Group 'SM pad to VIA (SAME sig) - reflow PRI'

SMp-Vp/r = ((8 -1 8 -1)(-1 8 -1 8)) ; SM pad to VIA (SAME sig) *

Parameter Group 'SM pad to Testpad - reflow SEC'

SMp-TP/r = ((20 20 20 20)(20 20 20 20)) ; SM pad to Testpad *

Parameter Group 'SM pad to CHIP pad - reflow PRI'

CHIPp-CHIPp/r = ((30 40 30 40)(40 30 40 30)) ; Chip pad to Chip pad *

Parameter Group 'SM pad to SMD & CHIP pad - reflow PRI'

Dp-SMp/r = ((30 30 30 30)(30 30 30 30)) ; SMD pad to CHIP & SMD pad *

Parameter Group 'SM pad to DPAK pad - reflow PRI'

DPAK-SMp/r = ((80 80 80 80)(80 80 80 80)) ; DPAK pad to SM pad *

Parameter Group 'SM pad to GW pad - reflow PRI'

GWp-GWp/r = ((30 30 30 30)(30 30 30 30)) ; Gull-Wing pad to Gull-Wing pad **

GWp-Dp/r = ((30 30 30 30)(30 30 30 30)) ; Gull-Wing pad to Discrete pad **

GWp-CHIPp/r = ((40 40 40 40)(40 40 40 40)) ; Gull-Wing pad to CHIP pad **

Parameter Group 'SM pad to SOJ pad - reflow PRI'

SOJp-SMp/r = ((60 60 60 60)(60 60 60 60)) ; SOJ pad to CHIP+Discrete pad **

SOJp-SOICp/r = ((100 100 100 100)(100 100 100 100)) ; Gull-Wing pad to SOJ pad **

SOJp-SOJp/r = ((150 150 150 150)(150 150 150 150)) ; SOJ pad to SOJ pad **

Parameter Group 'SM pad to QFP pad/body - reflow PRI'

PLCC-CHIP/r = ((60 60 60 60)(60 60 60 60)) ; PLCC to CHIP+Discrete **

PLCC-GWp/r = ((100 100 100 100)(100 100 100 100)) ; PLCC to Gull-Wing pad/body **

QFP-SM/r = ((100 100 100 100)(200 200 200 200)) ; QFP+CQUAD to SM **

PLCC-SM/r = ((200 200 200 200)(200 200 200 200)) ; PLCC to SM **

Parameter Group 'SM body to VIA - reflow PRI'

CHIPSb-V/r = ((0 0 0 0)(0 0 0 0)) ; Chip small body to Via *

CHIPLb-V/r = ((10 10 10 10)(10 10 10 10)) ; Chip large body to Via *

Parameter Group 'SM body to SM body - reflow PRI'

SMb-SMb/r = ((30 30 30 30)(30 30 30 30)) ; SM body to SM body *

GWb-CHIPb/r = ((30 30 30 30)(30 30 30 30)) ; Gull-Wing body to CHIP body **

GWb-SMDb/r = ((40 40 40 40)(40 40 40 40)) ; Gull-Wing body to SMD body **

GWb-GWb/r = ((40 40 40 40)(40 40 40 40)) ; Gull-Wing body to Gull-Wing body **

Parameter Group 'SM body to Testpad - reflow SEC'

SMb-TP/r = ((20 20 20 20)(20 20 20 20)) ; SM pad to Testpad *

Parameter Group 'SM body to TH body - reflow PRI'

StakePin-SM/r = ((75 75 120 85)(75 75 120 85)) ; SM to Stake-Pin *

Parameter Group 'VIA to VIA/TP - g+w SEC'

V-VTP/w = ((15 15 15 15)(15 15 15 15)) ; Via to Via/TestPad *

Parameter Group 'SM pad to VIA - g+w SEC'

SMp-V/g = ((40 20 40 20)(20 40 20 40)) ; SM pad to Via *

Parameter Group 'GW,SMD pad to VIA - g+w SEC'

GW+SMDp-V/g = ((20 20 20 20)(20 20 20 20)) ; Gull-Wing/Discrete pad to Via *

Parameter Group 'SM body to VIA - g+w SEC'

SMDb-V/g = ((20 20 20 20)(20 20 20 20)) ; SMD body to Via *

CHIPb-V/g = ((40 20 40 20)(20 40 20 40)) ; CHIP body to Via *

Parameter Group 'SM pad to Testpad - g+w SEC'

SMp-TP/g = ((20 20 20 20)(20 20 20 20)) ; SM pad to Testpad *

Parameter Group 'SM pad to SM pad - g+w SEC'

sCp-sCp/g = ((40 40 40 40)(40 40 40 40)) ; small Chip pad to small Chip pad *

lCp-SMp/g = ((50 50 50 50)(50 50 50 50)) ; CHIP/Discrete pad to CHIP/Discrete pad *

Parameter Group 'SM pad/body to Gull-Wing pad/body - g+w SEC'

GWp-CHIPp/g = ((100 100 100 100)(100 100 100 100)) ; Gull-Wing Pad/body to CHIP Pad/body **

Parameter Group 'SM pad/body to Gull-Wing pad/body - g+w SEC'

GWp-GWp/g = ((250 250 250 250)(250 250 250 250)) ; Gull-Wing Pad/body to Gull-Wing Pad/body **

Parameter Group 'SM body to SM body - g+w SEC'

sSMb-sSMb/g = ((40 40 40 40)(40 40 40 40)) ; CHIP/Discrete Body (small) to CHIP/Discrete Body (small) *

lSMb-SMb/g = ((50 50 50 50)(50 50 50 50)) ; CHIP/Discrete Body (large) to CHIP/Discrete Body *

Parameter Group 'SM pad/body to axial pad - g+w SEC'

SM-AXp/g = ((125 125 125 125)(125 125 125 125)) ; SM pad to AXial pad-center *

Parameter Group 'SM pad to radial pad - g+w SEC'

SM-RAp/g = ((125 125 125 125)(125 125 125 125)) ; Surface-Mount pad to RAdial pad-center *

Parameter Group 'SM body to Testpad - g+w SEC'

SMb-TP/g = ((40 40 40 40)(40 40 40 40)) ; SM body to Testpad *

Parameter Group 'Silkscreen checking'

MM = ((500 500 500 500)(500 500 500 500)) ; Silkscreen checking

Parameter Group 'Fiducial checking'

Fiducial = ((55 55 55 55)(55 55 55 55)) ; Fiducial quiet zone.

Parameter Group 'Exposed Copper checking'

Expo_Copper = NO ; Exposed Copper

Parameter Group 'Placement/Component'

TH/PRI = Yes ; Thruhole Component on Primary side only.

DevRot/SEC = Yes ; SM rotation as per SolderFlow Direction (g+w).

DevBlock/SEC = Yes ; DevBlock as per SolderFlow Direction (g+w).

Parameter Group 'Teardrop missing.'

TearDrop = Yes ; Teardrop missing.

Parameter Group 'Board_ID incomplete.'

Board/ID = Yes ; Board Identification is incorrect.

Parameter Group 'Pcode or Package not found in Corp.cd'

Pcode/TB = Yes ; Pcode or Package not found in Corp.cd

Parameter Group 'Pad's Integrity check.'

Signal/TP = Yes ; Logic signals must have at least 1 TestPad.

TP/Device = Yes ; TestPads under devices.

TP/SR = Yes ; TestPads do not have proper Solder_Resist.

TP/Integrity = ((40 40 40 40)(40 40 40 40)) ; TestPad too small or located on PRIMARY layer. *

SR/Pin = Yes ; Pin pad and Solder Resist do not match.

SO/Paste = Yes ; Pin pad and Solder Paste do not match.

Parameter Group 'Solder Stop check.'

SO/Stop = Yes ; Pin pad and Solder Stop do not match.

Notes:

* The 1st list is for devices with 0/180 degree rotation; the 2nd list is for devices with 90/270 degree rotation.

** The 1st list is for pins extended outside the device's body; the 2nd list is for device's body.

[UP] APPENDIX A

DEFINITION OF TERMS:

 SM ...................... All Surface Mount devices.

SM-0603 ............ CHIP 0603 package.

SM-1206 ............ CHIP 1206 package.

SM-1210 ............ CHIP 1210 package.

SM-1208 ............ CHIP 1208 package.

SM-1812 ............ CHIP 1812 package.

SM-2010 ............ CHIP 2010 package.

SM-2220 ............ CHIP 2220 package.

SM-2225 ............ CHIP 2225 package.

SM-2512 ............ CHIP 2512 package.

CHIP .................. Surface Mount 2 pin_devices (resistors, capacitors, etc).

CHIPS ................ Small size CHIP devices.

CHIPL ................ Large size CHIP devices.

SMD ................... Surface mount discrete devices (transistors, diodes,transformers, inductors, etc).

SOIC ................... Small Outline IC device (GullWing pin).

SMIC .................. Surface mount integrated circuits ( SOIC, SOJ, QFP, etc).

SOJ ..................... Small Outline IC devices (J-lead pin).

SOT .................... Small Outline Transistor devices.

SOD .................... Small Outline Diode devices.

SOP .................... Small Outline Package.

QFP .................... Quad Flat Pack IC devices.

PLCC ................. Plastic Leaded Chip Carrier devices.

C-QUAD ............ C-QUAD Quad Flat Pack IC devices.

D-PAK ............... SOT252 style transistor/diode devices.

AX ...................... Thruhole `s AXIAL.

RA ...................... Thruhole `s RADIAL.

PCB .................... Printed Circuit Board that all devices are mounted to.

Through hole ...... Devices that have lead(s) that extend through the PCB.

[UP] APPENDIX B

PARAMETER GROUPS & PARAMETERS FOR REFLOW MANUFACTURING PROCESS:

 SMp-CHIPp/reflow - SM pad to CHIP pad.

SMp-SMDp/reflow - SMD pad to SMD pad or SMD pad to CHIP pad.

SMp-DPAKp/reflow - SM pad to DPAK pad.

SMp-GWp/reflow - SM pad to Gull-Wing pad.

SMp-SOJp/reflow - SM pad to SOJ pad.

SMp-QFPp/reflow - SM pad to QFP pad.

SMb-SMb/reflow - SM body to SM body.

TH-SM/reflow - Thru-hole body to SM body.

SMp-TP/reflow - SM pad to TestPad.

SMb-TP/reflow - SM body to TestPad.

SMp-VIAp/reflow - SM pad to Via (SAME signal).

GWp-VIA/reflow - Gull-Wing pad to Via (Different signal).

CHIPLp-VIA/reflow - CHIP Large pad to Via.

SMp-VIA/reflow - SM pad to Via.

SMb-VIA/reflow - SM body to Via.

PARAMETER GROUPS & PARAMETERS FOR GLUE & WAVE MANUFACTURING PROCESS:

GWp-VIA/g+w - Gull-Wing/SMD pad to VIA.

SMp-VIA/g+w - SM pad to Via.

SMp-TP/g+w - SM pad to TestPad.

SMp-CHIP/g+w - SMIC body to CHIP/SMD pad/body.

SMp-GWp/g+w - Gull-Wing Pad/body to Gull-Wing Pad/body.

SMp-SMp/g+w - CHIP/SMD Pad to CHIP/SMD Pad.

SMb-VIA/g+w - CHIP/SMD body to Via.

SMb-TP/g+w - SM body to TestPad.

SM-AXp/g+w - SM Pad/Body to Axial Pad.

SM-RAp/g+w - SM Pad to RADIAL Pad.

SMb-SMb/g+w - CHIP/SMD Body to CHIP/SMD Body.

VIA-VIATP/wave - VIA to VIA/TP.

PARAMETER GROUPS & PARAMETERS FOR OTHERS:

 Silkscreen/missing - Silkscreen Checks.

Exposed/Copper - Exposed Copper Checks.

Placed/Component - Component Placement checks.

FiducialCHK - Fiducial Checks.

Board_ID - Layout's Board Identification is incomplete.

PcodeTB - Pcode or Package not found in Corp.cd.

TearDrop - TearDrop/Missing.

Pad - Pad's Integrity checks.

[UP] APPENDIX C

SAMPLE VIOLATION REPORT:

 ntbx27aa.mets.rep Mon Jan 27 10:47:07 1997

METSver 5.00C

Parameter's file used: ntbx27aa.mets.parameter

Design:ntbx27aa Project:DMS-100 Designer:CHU/RAJWANI

Technology:RW04DS02

PCB Pec:NTBX2701 Cpc:P0702327 Rel:08 StrIss:0402 Size:3.5x2.9

SM devices : 58

TH devices : 15

SM pads : 241

TH pads : 93

Total Pins : 379

Vias : 118 (includes Misc pads and pins)

Testpads : 152

Total_items : 1056

Total Run_Time (Second): 53.52

Total Violations : 95

Max Height : 700.0 (Device: RN1)

Parameter

verified Description

----------- --------------------------------------

V-VTP/w - Via to Via/TestPad

SMp-V/g - SM pad to Via

GW+SMDp-V/g - Gull-Wing/Discrete pad to Via

SMDb-V/g - SMD body to Via

CHIPb-V/g - CHIP body to Via

SMp-TP/g - SM pad to Testpad

sCp-sCp/g - small Chip pad to small Chip pad

lCp-SMp/g - CHIP/Discrete pad to CHIP/Discrete pad

GWp-CHIPp/g - Gull-Wing Pad/body to CHIP Pad/body

GWp-GWp/g - Gull-Wing Pad/body to Gull-Wing Pad/body

sSMb-sSMb/g - CHIP/Discrete Body (small) to CHIP/Discrete Body (small)

lSMb-SMb/g - CHIP/Discrete Body (large) to CHIP/Discrete Body

SM-AXp/g - SM pad to AXial pad-center

SM-RAp/g - Surface-Mount pad to RAdial pad-center

SMb-TP/g - SM body to Testpad

SMp-V/r - SM pad to Via (All)

SMp-V0603/r - SM pad to Via (0603)

SMp-V0805/r - SM pad to Via (0805)

SMp-Via/r - SM pad to Via (1206)

GWp-VIA/r - GW pad to Via

SMp-V1808/r - SM pad to Via (1808)

SMp-V1210/r - SM pad to Via (1210,2010)

SMp-V1812/r - SM pad to Via (1812,2512)

SMp-V2220/r - SM pad to Via (2220)

SMp-V2225/r - SM pad to Via (2225)

SMp-Vp/r - SM pad to VIA (SAME sig)

SMp-TP/r - SM pad to Testpad

CHIPp-CHIPp/r - Chip pad to Chip pad

Dp-SMp/r - SMD pad to CHIP & SMD pad

DPAK-SMp/r - DPAK pad to SM pad

GWp-GWp/r - Gull-Wing pad to Gull-Wing pad

GWp-Dp/r - Gull-Wing pad to Discrete pad

GWp-CHIPp/r - Gull-Wing pad to CHIP pad

SOJp-SMp/r - SOJ pad to CHIP+Discrete pad

SOJp-SOICp/r - Gull-Wing pad to SOJ pad

SOJp-SOJp/r - SOJ pad to SOJ pad

PLCC-CHIP/r - PLCC to CHIP+Discrete

PLCC-GWp/r - PLCC to Gull-Wing pad/body

QFP-SM/r - QFP+CQUAD to SM

PLCC-SM/r - PLCC to SM

CHIPSb-V/r - Chip small body to Via

CHIPLb-V/r - Chip large body to Via

SMb-SMb/r - SM body to SM body

GWb-CHIPb/r - Gull-Wing body to CHIP body

GWb-SMDb/r - Gull-Wing body to SMD body

GWb-GWb/r - Gull-Wing body to Gull-Wing body

SMb-TP/r - SM pad to Testpad

StakePin-SM/r - SM to Stake-Pin

MM - Silkscreen checking

Fiducial - Fiducial quiet zone.

Expo_Copper - Exposed Copper

TH/PRI - Thruhole Component on Primary side only.

DevRot/SEC - SM rotation as per SolderFlow Direction (g+w).

DevBlock/SEC - DevBlock as per SolderFlow Direction (g+w).

TearDrop - Teardrop missing.

Board/ID - Board Identification is incorrect.

Pcode/TB - Pcode or Package not found in Corp.cd

Signal/TP - Logic signals must have at least 1 TestPad.

TP/Device - TestPads under devices.

TP/SR - TestPads do not have proper Solder_Resist.

TP/Integrity - TestPad either too small or located on PRIMARY layer.

SR/Pin - Pin pad and Solder Resist do not match.

SO/Paste - Pin pad and Solder Paste do not match.

SO/Stop - Pin pad and Solder Stop do not match.

/r indicates reflow process check

/w indicates wave process check

/g indicates glue & wave process check

Ref Lay Spec Meas Parameter Obj1X Obj1Y Obj1 Pin Obj2X Obj2Y Obj2 Pin

--- --- ----------------------------- ---- ------------- ----- ----- ---- ---- ----- ----- ---- ----

1 SEC 0 0 TP/Device -1800 550 Y1 -1800 358 TP74

2 SEC 0 0 DevBlock/SEC -850 2375 R4 -850 2375 R4

3 SEC 0 0 TH/PRI -2350 50 TP25 -2350 50 TP25

4 PRI ((55 55 55 55) (55 55 55 55)) 0 Fiducial -2054 223 oFiducial -2050 175 VIA

5 MMS ((0 0 0 0) (0 0 0 0)) 0 MM -2900 1200 TP23 -2900 1200 TP23

6 PRI ((10 10 10 10) (10 10 10 10)) 0 CHIPLb-V/r -900 2300 C1 -1000 2150 VIA

7 PRI ((10 10 10 10) (10 10 10 10)) 0 CHIPLb-V/r -1950 1275 C2 -1850 1355 VIA

8 PRI ((10 10 10 10) (10 10 10 10)) 0 CHIPLb-V/r -1300 1450 C3 -1400 1350 VIA

9 SEC ((20 20 20 20) (20 20 20 20)) 0 GW+SMDp-V/g -1545 175 D11 3 -1599 121 VIA

10 SEC ((40 20 40 20) (20 40 20 40)) 0 SMp-V/g -2363 935 C12 1 -2425 876 VIA

11 SEC ((15 15 15 15) (15 15 15 15)) 0 V-VTP/w -2400 2150 VIA -2351 2101 TP51

12 SEC ((50 50 50 50) (50 50 50 50)) 0 lCp-SMp/g -1705 2200 D5 3 -1800 2100 TP12 1

13 SEC ((50 50 50 50) (50 50 50 50)) 0 lSMb-SMb/g -1500 175 D11 -1600 300 TP24

14 SEC ((40 40 40 40) (40 40 40 40)) 0 sSMb-sSMb/g -2500 2385 C6 -2400 2500 TP2

15 SEC ((40 40 40 40) (40 40 40 40)) 0 sSMb-sSMb/g -2500 2385 C6 -2500 2500 TP1

Column Naming Definitions:

Ref - the violation number (for reference purposes)

Lay - the layer the violation is on

Spec - the spec dim req per 5015 or user defined

Meas - the dimension measured by the tool

Parameter - the name of the parameter being measured

Obj1X - the X coordinate for the 1st obj listed in the parameter name

Obj1Y - the Y coordinate for the 2nd obj listed in the parameter name

Obj1 - the design name of the first object

Pin - the associated pin #, if applicable, of the 1st obj

Obj2X - the X coordinate for the 2nd obj listed in the parameter name

Obj2Y - the Y coordinate for the 2nd obj listed in the parameter name

Obj2 - the design name of the second object

Pin - the associated pin #, if applicable, of the 2nd obj

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